1. Field of the Invention
The present invention is directed generally to transistors and more specifically to a method for manufacturing lateral bipolar transistors in silicon.
2. Description of the Related Art
A layer sequence for emitter, base and collector vertically arranged above one another is standard in integrated bipolar transistors. In this vertical arrangement, two zones of the layer sequence are not directly accessible from the surface, but must be laterally lengthened and subsequently conducted to the surface. A further, highly doped buried layer is generally also necessary for the lowest, doped layer in order to keep the lead to the surface of an adequately low impedance. The actual transistor, i.e. the npn or pnp sequence of the layers is not photolithographically defined, but is defined by diffusion processes and implantations, so that dimensions in the sub-.mu.m range can be achieved without problems. The disadvantage of this arrangement is that vertical transistors have a noteworthy depth expanse, typically 1-2 .mu.m, and lateral dimensions that exceed the actual transistor region by a multiple. Correspondingly, there are a number of parasitic capacitances and resistances that, in addition to causing possible losses in the switching speed, noticeably increase the power consumption. In addition, the complexity of the manufacturing process and the area requirements of these components are extremely high compared to MOS components causing low yields and high manufacturing costs. The simultaneous manufacture of complementary structures (npn and pnp transistors), for example for analog applications, is possible only with substantial outlay.
Given laterally arranged bipolar transistors, the regions for emitter and collector are usually embedded in a larger base region, so that these transistors also have a relatively large expanse in depth. A simple manufacturing method for such lateral transistors is still unknown.